The present invention relates to a method of forming patterned metal films wherein the pattern includes submicron-dimensioned features. The present invention of particular utility in integrated circuit semiconductor device manufacture, and is especially adapted for use in "back-end" processing for forming multiple levels of in-laid metallization patterns.
The escalating requirements for high density and performance associated with ultra large-scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing submicron-dimensioned (e.g., below about 0.18 .mu.m), low RC time constant metallization patterns, particularly wherein the submicron-sized metallization features such as vias, contact areas, grooves, trenches, etc., have high aspect (i.e., depth-to-width) ratios due to the increasing demands of microminiaturization.
The present invention is applicable in manufacturing various types of semiconductor devices, such as the type illustrated in FIG. 1, which comprises a semiconductor wafer substrate, usually of doped monocrystalline silicon (Si), having at least one active device region or component (e.g., an MOS type transistor, a diode, etc.) formed therein or thereon, and a plurality of sequentially formed inter-layer dielectrics (ILDs) and patterned conductive layers (METALs) formed therein and/or therebetween. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnection lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced apart metallization layers are electrically interconnected by a substantially vertically oriented conductive plug (termed "VIA") filling a via hole formed in the ILD separating the metallization layers, while another conductive plug filling a contact area hole establishes ohmic contact with an active region (e.g., a source/drain region of an MOS type transistor) formed in or on the semiconductor substrate. Conductive lines formed in groove or trench-like openings in overlying dielectric layers extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type as illustrated in FIG. 1 and fabricated according to current technology may comprise five or more levels of such metallization in order to satisfy device geometry and miniaturization requirements.
Electrically conductive films or layers of the type used in "back-end" semiconductor manufacturing technology as required for fabrication of devices such as described above and illustrated in FIG. 1 typically comprise a metal such as titanium, tantalum, tungsten, molybdenum, aluminum, chromium, nickel, cobalt, palladium, silver, gold, copper, and their alloys. However, conventional methodology for performing "back-end" metallization processing utilizing any of the enumerated metals presents several disadvantages and drawbacks. Specifically, such conventional "back-end" processing is complex, difficult, costly, time consuming, and entails a significant reduction in interconnection reliability and product yield as feature sizes decrease and the number of metallization levels increases. For example, a typical damascene-type process performed according to the conventional art for forming a single via/metallization pair can involve as much as forty (40) separate processing steps, including, inter alia, formation of a photoresist layer on a first dielectric layer; selective exposure of the photoresist through a patterned mask; development of the exposed photoresist to form a patterned photoresist; selective etching of the patterned resist-coated dielectric layer to form a via hole pattern therein; filling of the via holes with metal plugs; deposition and planarization of a dielectric gap-fill layer to form a second dielectric interlayer; photoresist formation thereon; selective exposure and development of exposed photoresist to form a pattern of openings or recesses therein corresponding to the desired metallization pattern; filling of the recesses with the selected metal, including formation of a blanket or overburden layer of excess thickness to ensure complete filling of the recesses; removal of the blanket or overburden layer; and planarization of the remaining dielectric layer surface to form an in-laid metallization pattern. Inasmuch as the formation of each additional via/metallization pair adds an additional approximately forty (40) process steps, it is evident that repetition of the above-described sequence of steps up to, e.g., fifteen (15) times, for forming high integration density, multi-metallization level semiconductor devices, entails significant cost, great manufacturing complexity, and increased likelihood of occurrence of defects and reliability problems, as well as reduced product yield. Furthermore, non-damascene type processes for forming in-laid metallization patterns, e.g., processes comprising blanket deposition of metal layers, selective removal thereof by means of photolithographic masking and etching techniques to define desired metallization patterns therein, dielectric gap-fill layer deposition, and planarization thereof, are equally difficult, complex, expensive, and subject to the above-enumerated drawbacks associated with damascene-type processing, including increased likelihood of defect formation, and reduced reliability and product yield.
Thus, there exists a clear need for an efficient, simplified method for forming multiple levels of in-laid "back-end" metallization patterns at reduced cost, increased reliability and product yield, and which does not entail the complexity and drawbacks associated with conventional in-laid metallization processing. Specifically, there exists a need for an improved method of forming such metallization patterns in submicron-sized dimensions, for forming contacts, vias, interconnection routings, etc., which method is fully compatible with conventional process flow and methodology in the manufacture of ultra large-scale, high integration density integrated circuit semiconductor devices.
The present invention fully addresses and solves the above described problems and drawbacks attendant upon conventional processing for manufacturing integrated circuit semiconductor devices requiring multiple metallization levels, particularly in providing a very significant, dramatic reduction in the number of requisite processing steps from about 40 to about 8 for each via/metallization pair, thereby significantly reducing manufacturing costs, increasing product reliability and yield, and dramatically increasing production throughput. These significant advantages are achieved while providing full compatibility with the balance of device manufacturing process flow and methodology.